Lab Two

Lab 421 - Digital Integrated Circuit Design

Authored by Moriah Wingrove

Due: September 4 2019

Lab Two Description:

Prelab Two:

All coursework and labwork was backed up. The archive containing the simulation example of an ideal 10-bit Analog-to-Digital converter and Digital-to-Analog converter was downloaded to my desktop. After the download was complete the file was uploaded and unzipped into my design directory CMOSedu on Cadence.

Cadence was opened and the schematic view of the cell sim_Ideal_ADC_DAC was selected. Once the schematic was open the simulation was run to obtain the following.

The least significant bit is determined by using 1LSB =Vref/(2^N)

For the given schematic Vref = 5V and N = 10
                                   1LSB = 5V/2^10
                                    1LSB = 5V/1024
                                    1LSB = 4.883mV

The schematic was then modified so that the amplitude was 3V with an offset of 6V. The value of Vin is expected to be 9V. Vout is determined by F*Vref. F = D/(2^N) with D being the input word which is N bits long. In the simulation below the measure Vout value is clipped at 5V since the voltage cannot surpass the reference value of 5V.

The modified schematic is pictured below on the left with the simulation results on the right.

Lab:

For the lab a 10-bit DAC was designed using 10k resistors.

The above images are of the entire 10-bit DAC design using 10k resistors and the zoomed in image showing the resistor values.

The output resistance of the DAC can be determined by combining the resistors in series and in parallel. The output resistance can be determined by using superposition on the circuit. If all the bits except B9 are grounded the bottom resistors are in parallel. When evaluated the equavalent resistance is R. The value of R used is 10k. The resistance is then in series with another resistor R and in parallel with 2R. This can be done for all 10-bits and the output resistance value equals R. When all of the bits except B9 are grounded the circuit is a voltage divider and Vout = B9*(2R//2R) = 1/2*B9. The voltage output for the other inputs can be determined by using Vout = VDD/2^N, where VDD is the voltage input and N is the bit. As some examples, B9 Vout = VDD/2^0 =1/2VDD, B0 = VDD/2^10 = VDD/1024, and B3 = VDD/2^7 = VDD/128.

The delay of the DAC with a 10pF load is 70ns.

Above image showing symbol of 10-bit DAC with B9 input connected to a pulse with all other inputs grounded and 10pF load.

The above image shows the simulation results of the DAC with Hand calculations for the delay of the DAC
the 10pF load. The delay time is measured at 70ns. with a 10pF load

Since the design doesn't use VDD, Verfp, or Vrefm the pins for those three were deleted and the symbol was updated. After the symbol was updated the simulation for the delay with a 10pF was resimulated to ensure the same results were obtained. Below are the images for the updated symbol, the schematic for the DAC with a 10pF load, and the simulation of the schematic showing the same results were obtained.

The design for the DAC was used to replace the ideal DAC in the given ADC_DAC schematic. The simulation for the ideal ADC_DAC is simulated below along with the designed ADC_DAC simulation to show the design works as expected.

Simulation of ideal ADC_DAC Simulation of designed ADC_DAC

Resitor Load:

If the DAC drives a load of 10k the amplitude of the output voltage is halved. The output resistance of the DAC was determined earlier to be 10k is in parallel with the 10k load. This causes the DAC to act as a voltage divider with the amplitude of the output equal to 1/2 * Vin.

Schematic of the ADC_DAC circuit driving a 10k load Simulation of the ADC_DAC circuit driving a 10k load

Capacitor Load:

If the DAC drives a load of 10pF it can be observed that the output lags the input by 70ns. The maximum input of 5V occurs at 125ns and the maximum of the output voltage 4.13V occurs approximately 70ns later at 195ns.

Capacitor & Resistor Load:

If the DAC drives a load of 10pF and 10k.The input reaches a peak voltage of 5V. After going through the RC load the output voltage has a peak of 2.3V. The delay between the output and the input is 50ns.

If the resistance in the switches on a real circuit was not small compared to R than the overall resistance of the designed DAC would increase. In our design the resistance of the switches was negligible allowing our DAC output resistance to be R. If the restance of each switch was larger than the output resistance of the DAC would increase and the output voltage would dissipate at a faster rate.

Backing it up

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